The present system relates generally to communication between digital processors in a multiprocessor computer system and, more particularly, to a protocol for a multiprocessor bus.
Many digital computer systems are using a plurality of independent processors to perform computer operations. Examples include fault-tolerant modular, and parallel processing systems. These independent processors need to exchange data from time to time, to perform system operations.
Typically data is exchanged between processors on a bus. The protocol of the multiprocessor system controls access by processors to the bus, facilitates the formation of a sender/receiver pair of processors, and provides a timing reference for transferring data from the sender to the bus and from the bus to the receiver.
In many existing systems a dedicated bus controller is coupled to the bus and functions to poll the processors to determine which processors are ready to send data. Typically, the poll for senders sequence is instigated by a processor that is ready to send signalling the bus controller on a dedicated line common to all processors.
The bus controller determines which processors are ready to send by serially polling the processors on dedicated select lines.
In one example of a multiprocessor bus protocol disclosed in U.S. Pat. No. 4,228,496 to Katzman et al., the bus controller then begins a data exchange by enabling the sender. This enablement is accomplished via the individual select line to the sender. The sender then acknowledges if ready. The bus controller enables the receiver via the individual select line to the receiver. If the receiver is ready to receive data, then it signals the bus controller with an acknowledge signal.
In the Katzman system, the bus transfer is synchronized by the system clock. This clock signal is supplied to each processor by individual clock lines. These lines are all the same length so the clock signal arrival times at each processor are not skewed.
The period of system clock signal must be long enough to allow propagation of a signal between processors positioned at opposite ends of the bus and to allow for the bus settling times. Accordingly, the maximum data transfer rate is determined by the length of the bus.
A primary objective of any multiprocessor bus protocol is to provide a high rate of data transfer between processors via the bus. Several aspects of existing protocol systems prevent the attainment of high data transfer rates. First, the requirement of generating a sender request before a poll, sender acknowledges, and receive acknowledge before a transfer generates bus overhead time. Secondly, the synchronous transfer system requires that data be valid on the entire bus before being transferred to a receiver because the location of the receiver may be anywhere on the bus. Thus, the maximum data transfer rate is determined by the propagation delay of signals propagating the length of the bus.
Additionally, the need to provide separate clock lines, of equal length, and individual select lines to each processor requires a large number of wires to form the bus thereby, increasing the manufacturing complexity and expense of the bus hardware.